A high efficiency straightforward design and verification methodology for PLL systems

This paper presents a straightforward top-down design methodology for frequency synthesizer systems, where the PLL noise shaping can be directly transformed from time-discrete domain to the event-driven phase domain. Compared to conventional PLL modeling methodologies, the PLL noise sources from various components and analog mismatch can be described both in abstract and behavior level. The simulation efficiency is significantly improved in the transceiver level, which completes the bottom-up verification flow with precise PLL modeling including noise contribution from various sources. Therefore, the proposed methodology provides an efficient approach for an entire mixed-signal transceiver system verification.