Effect of different design stages on the SEU failure rate of FPGA systems

This work analyzes the effect of the different design stages on the failure rate of circuits implemented in FPGAs. A bitstream-based SEU emulation platform is used to inject faults in order to analyze the critical bits of the circuit. Experiments are done on two different testbenchs, an FIR filter and a CORDIC chain. Tests consist on loading different variations of the designs in order to estimate the effect of different design parameters on the failure rate. Parameters of different design stages such as source generation, synthesis and implementation are analyzed. It has been observed that the implementation process can add a huge variation to the failure rate. This has an impact on design validation and points out that validation techniques applied at early design stages previous to implementation can be inaccurate. It has also been observed that the effect is more notorious for regular circuits containing many time critical nets.