A Design And Implementation Of 32-Paths Parallel 256-Point Fft/Ifft For Optical Ofdm Systems

This paper presents the design and implementation of thirty-two paths parallel FFT/IFFT for optical OFDM systems. Employing OFDM over high speed optical transmission systems requires large hardware resources due to computational-intensive operations such as full-parallel FFT implementation. The proposed 256-point FFT/IFFT adopts 32-paths parallel architecture with mixed radix-23 and radix-25 algorithm to reduce large number of complex multipliers. With this architecture, 256 full parallel data signals can be divided into eight sequential groups. Each group, composed of 32 parallel signals, is pipeline-processed. As a result, the hardware resources for full parallel 256-point FFT operation can be reduced to as much as those of 32-point FFT resource plus 32-path 8-point single-path delay feedback (SDF). The proposed FFT architecture is implemented with field programmable gate array and integrated in 12 Gbps, 64-QAM encoded real-time optical OFDM system. The implementation result shows that an 86% complex multiplier reduction can be achieved in comparison with full parallel architecture. The attained error vector magnitude (EVM) is approximately up to -32 dB for 64-QAM OFDM signals.