Radiation Damage In Transistors Fabricated With Lapis Semiconductor 200 Nm Fd-Soi Technology

The paper presents radiation tolerance of the transistor TEG (TrTEG5) test structure fabricated in 200 nm fully depleted silicon on insulator technology dedicated to production of SOI detectors. The chip was irradiated with 60 Cobalt gamma-ray source to total dose of 1.175 kGy at a rate of 67.8 Gy/h. During irradiation, current-voltage characteristics of seventeen different transistors were measured so as to investigate factors affecting radiation resistance. Transistors' threshold voltage shift and transconductance change as a function of the deposited dose are presented. After irradiation all transistors manifested correct operation and threshold voltage change of around 200 mV fall within the limits of specified technological mismatch.