7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

Tomoharu Tanaka,Mark Helm,Tommaso Vali,Ramin Ghodsi,Koichi Kawai,Jae-Kwan Park,Shigekazu Yamada,Feng Pan,Yuichi Einaga,Ali Ghalam,Toru Tanzawa,Jason Guo,Takaaki Ichikawa,Erwin Yu,Satoru Tamada,Tetsuji Manabe,Jiro Kishimoto,Yoko Oikawa,Yasuhiro Takashima,Hidehiko Kuge,Midori Morooka,Ali Mohammadzadeh,Jong Kang,Jeff Tsai,Emanuele Sirizotti,Eric Lee,Luyen Vu,Yuxing Liu,Hoon Choi,Kwonsu Cheon,Daesik Song,Daniel Shin,Jung Hee Yun,Michele Piccardi,Kim-Fung Chan,Yogesh Luthra,Dheeraj Srinivasan,Srinivasarao Deshmukh,Kalyan Kavalipurapu,Dan Nguyen,Girolamo Gallo,Sumant Ramprasad,Michelle Luo,Qiang Tang,Michele Incarnati,Agostino Macerola,Luigi Pilolli,Luca De Santis,Massimo Rossini,Violante Moschiano,Giovanni Santin,Bernardino Tronca,Hyunseok Lee,Vipul Patel,Ted Pekny,Aaron Yip,Naveen Prabhu,Purval Sule,Trupti Bemalkhedkar,Kiranmayee Upadhyayula,Camila Jaramillo

2016 IEEE International Solid-State Circuits Conference (ISSCC)（2016）

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摘要

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3–5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.

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关键词

3D-floating-gate NAND flash memory,memory density,3D memory cell,charge-trap cells,3D floating gate technology,size 16 nm

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