Characterization of half-pitch 15-nm metal wire circuit fabricated by directed self-assembly of polystyrene-block-poly(methyl methacrylate)

We developed a novel but simple sub-15-nm line-and-space (L/S) patterning process that requires neither special pinning guide materials to control the surface free energy nor a resist strip process after the guideline pattern fabrication. To perform process verification for practical semiconductor device manufacturing, we demonstrated electrical yield verification of the process and analyzed the causes of the process defects. One of the causes of open defects is narrower spaces in the upper layer. Improvements in the narrow space points originated from the critical dimension (CD) uniformity, and the roughness at the upper layer is effective for reduction of open defects. The radiofrequency (RF) power in pulsed mode and the depo-etch sequence in the reactive ion etching (RIE) process are effective in improving the surface roughness at the upper layer.