谷歌浏览器插件
订阅小程序
在清言上使用

Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits

IEEE Transactions on Components, Packaging and Manufacturing Technology(2019)

引用 4|浏览4
暂无评分
摘要
In this paper, we present “Cool Interconnect,” a 1024-bit wide bus that we have developed to provide a standardized method of interconnecting chips in 3-D integrated circuits (3DICs). This wide bus chip-to-chip interconnect can be used to realize low-power high-performance multicore systems to meet the increasing demand for advanced electronics to enable autonomous vehicles and Internet of Things devices. The bus has been implemented using a $40\times 40$ fine-pitch array of through-silicon vias and bump joints. In addition, we have developed a testing methodology based on the boundary scan method to confirm the electrical performance of wide bus chip-to-chip interconnect in 3DICs. Cool Interconnect test chips were designed, fabricated, and flip-chip stacked. Joint Test Action Group (JTAG) and electrical connection tests were used to confirm the successful operation of the test chips, including the chip-to-chip interconnect.
更多
查看译文
关键词
Three-dimensional displays,Integrated circuit interconnections,Stacking,Through-silicon vias,Standards,Performance evaluation,Power demand
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要