Scaling of Split-Gate Flash Memory with 1.05V Select Transistor for 28 nm Embedded Flash Technology

Nhan Do, J.W. Yang, Y. J. Sheng, C. S. Su, M. T. Wu, H. Ouyang, H. Liang,S. Hariharan, M. Tadayoni, J. Norman,T. Vu,A. Ly,S. Hong,H. Tran,V. Tiwari,C.H. Chen, T.F. Ou, C.C. Shih

2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW)（2018）

Cited 3|Views11

No score

Abstract

This paper discusses the performance and reliability of the third generation split-gate flash memory cell (ESF3) successfully embedded in a high performance and low power 28 nm logic process technology. The scaling of the 1.05V select transistor is demonstrated with the excellent program and erase efficiency and the 1M program/erase (P/E) cycle endurance capability. The silicon result of a 4Mb test chip and a 32Mb design will be also be shown.

Translated text

Key words

reliability,ESF3,test chip,erase efficiency,low power logic process technology,high performance logic process technology,third generation split-gate flash memory cell,program-erase cycle endurance capability,embedded flash technology,select transistor,size 28.0 nm,voltage 1.05 V,storage capacity 4 Mbit,storage capacity 32 Mbit

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined