Reliability engineering: Help enable technology scaling

The paper discusses many aspects of reliability engineering, modeling, and characterization methods that could be used to improve reliability of the technology. As results, higher transistor Vmax or reduced dppm, more tolerable aging at the circuit and/or product level can be utilized by accurate wafer level reliability characterization and modeling. On the BEOL and far-BEOL, EM and BEOL metal-via spacing requirements will be discussed with areas where improvements can be made with help of simulation and low voltage stress data. CPI stress results will also be covered. Product level reliability stack up is assessed to provide more accurate dppms projections. Extra reliability margins could be applied for further dimension scaling, or upfront commit for technology development, increasing over-drive to achieve higher performance where needed and also to support different grade levels for automotive applications.