Development of a new high-speed readout system for SOI pixel detectors

We are developing a new high-speed readout system for silicon on insulator (SOI) pixel detectors. The SOI detector is a monolithic radiation imaging detector based on a 0.2 μm FD-SOI CMOS process. Previously, we used a Xilinx Virtex-4/5 FPGA readout board for the SOI detector and developed many facilities for this board. However, the Virtex-4/5 FPGA is now obsolete and does not have sufficiently high performance for recent experiments that require more than 1-kHz high-speed imaging with a large number of pixels. Thus, we started to develop a new high-speed readout system using the KC705, which is the evaluation board for the Xilinx Kintex-7 FPGA. We developed a new data acquisition structure that has backward compatibility with the previous environment on this board and implements several functions for practical purposes such as micro Computed Tomography. The transfer speed achieved by the new system is 95.3 fps for a 426k pixel detector in continuous data-taking mode, and 762.5 fps in maximum-speed mode. The details of the new readout system are presented.