3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

Wen-Wei Shen,Yu-Min Lin,Shang-Chun Chen,Hsiang-Hung Chang,Tao-Chih Chang,Wei-Chung Lo,Chien-Chung Lin,Yung-Fa Chou,Ding-Ming Kwai,Ming-Jer Kao,Kuan-Neng Chen

IEEE Journal of the Electron Devices Society（2018）

Cited 11|Views30

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Abstract

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-μm-diameter/50-μm-length) and Cu interco...

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Key words

Random access memory,Bonding,Through-silicon vias,Three-dimensional displays,Stacking,Silicon,Substrates

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