A 50gb/S-Pam4 Cdr With On-Chip Eye Opening Monitor For Reference-Level And Clock-Sampling Adaptation

Liu Chang,Bozhi Yin,Tingyu Yao,Nan Qi,Dan Li,Jingbo Shi,Juncheng Wang,Hu Shang,Rui Bai,Patrick Chiang

2018 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXPOSITION (OFC)（2018）

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摘要

A 50Gb/s-PAM4 Clock/Data Recovery (CDR) transceiver is designed in a 40nm-CMOS process. An on-chip Eye Opening Monitor (EOM) is introduced that enables adaptive reference level and timing sampling placement for non-uniform and distorted PAM4-inputs.

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关键词

Clock-sampling adaptation,CMOS process,PAM CDR,clock-data recovery transceiver,on-chip eye opening monitor,EOM,distorted PAM4-inputs,timing sampling placement,adaptive reference level,size 40.0 nm,bit rate 50 Gbit/s

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