Layered T Parity Generators Using Quantum-Dot Cellular Automata

Mohit Agarwal,Abhijit Das,Subham Kumar, Swaniket Chowdhury,Lalbabu Kumar,Chiradeep Mukherjee,Sayak Pramanik,Dipta Mukherjee,Uttam Narendra Thakur

2017 8TH IEEE ANNUAL INFORMATION TECHNOLOGY, ELECTRONICS AND MOBILE COMMUNICATION CONFERENCE (IEMCON)（2017）

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Abstract

The Parity Generators and checkers are crucial block in Central Processing Unit especially in the process of Error Detection and correction during data transmission. In this work, the three-bit Quantum Cellular Automata (QCA) even parity generator have been proposed using Layered T AND and OR Gate. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. Moreover, the other QCA design metrics such as Effective Area, O-Cost, Costa, Irreversible Power Dissipation, and Complexity are analyzed for the proposed Parity Generator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner.

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Key words

Layered T Gate, Parity Generators, Cost(alpha), Quantum-dot Cellular Automata

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