A 1.1- $\mu \text{m}$ 33-Mpixel 240-fps 3-D-Stacked CMOS Image Sensor With Three-Stage Cyclic-Cyclic-SAR Analog-to-Digital Converters

In this paper, a 1.1-μm-pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the interc...