Experimental Demonstration Of 1024-Ifft Fpga Implementation With 3.98 Gbps Throughput For Co-Ofdma-Pon Transmitters

This work presents a design and implementation of inverse fast Fourier transform (IFFT) for coherent optical orthogonal frequency division multiple access passive optical network (CO-OFDMA-PON) using a field-programmable gate array (FPGA). The IFFT size of 1024 is considered. The core computation is forward FFT processing. The tested hardware consists of a digital-to-analog converter (DAC) with the sampling rate of 500 Msps and the FPGA form Xilinx ML605 evaluation board. The FPGA is the key computation. For the IFFT calculation topology, the Radix-4 with 4 parallel processing units is employed. As a result, 16 inputs are calculated at the same time. By employing parallel processing, the internal FPGA clock is reduced to only 31.25 MHz (=500/16 MHz). Additionally, in this work, 256-QAM is perfectly adopted. Consequently, the net speed up to 3.98 Gbps throughput can be achieved. The hardware resources usage is