Compact delay matching solution for reference clock in PCB
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)(2017)
Abstract
This paper proposes a compact delay matching solution for reference clock in PCB. The proposed method provides up to 70% area saving compared to the traditional length matching methods. It also provides design and layout flexibility. Effectiveness of the matching network, electrical static performance, and component variation impacts are simulated and compared to conventional methods.
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Key words
clock,PCB,area saving,compact delay component
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