Statistical accuracy analysis of complex floating point multipliers

Scalar addition and multiplication generally obey commutative and distributive laws. However, in their hardware implementation, error propagation and accumulation do not necessarily follow the same rules. In this paper we present a statistical analysis of the accuracy in complex multiplication approaches for IEEE 754 single precision operands. Several approaches were evaluated using a dual approach that included an error analysis of the multiplication operator architectures and a statistical analysis of VHDL operator designs, implemented on a Xilinx Virtex 7 FPGA. Multiple experiments were carried for systematically assessing architectural, synthesis, and hardware performance characteristics of the target designs, comparing weaknesses and strengths of each architecture.