Thermal-stress co-simulation of a Ka-band millimeter-wave T/R System in Package

Thermal-stress co-simulated of a mm-wave T/R system in package(SiP) for Ka-band radar, was performed using ANSYS Workbench code. the T/R SiP is base on four layer high-resistivity silicon substrates which is stacked layer by layer, thermal flux generated from chips propagated to aluminium alloy cavity through silicon substractes and a molybdenum-copper plate. In simulation, the thermal power of the amplify is set as 3.3 Watt, the power of the three frequency multipliers and the three LNAs are 0.9 Watt and 0.625 Watt per chip respectively, the whole tharmal power of the seven chips is about 7.9W. Transient thermal analysis also was performed, the simulated result shows that the tempreture of the SiP rises to steady state at about one thousand seconds after work start, the highest tempreture in the SiP is about 60°C and the hot point is localed on the power amplify chip. Thermal-stress also was simulated under the steady-tempreture distribution, the maximum stress is 682MPa and locates at the edge of the molybdenum-copper plate, this is caused by the large difference of thermal expansion coefficient between the molybdenum-copper and the aluminium alloy material. The stress in silicon baseboard caused by warping is a most potential crack risk in the SiP, the maximum stress in the sillicon baseboard is about 136MPa, it locates at the top edges of the silicon MEMS cavities for embeding chips, and the stress is below the crack strength of the silicon material. The normal stress on the bonding regions between adjacent silicon layers ranges from 13MPa to 40MPa, which isn't exceeds the stacked bonding strength. From the simulation, the thermal and structure relibility of the SiP was checked, which is conducive to reduce failure risk during SiP works.