Digital PLL design challenges for cellular RFICs

Sangsoo Ko,Chih-Wei Yao,Joonhee Lee,Sangwook Han,Daehyeon Kwon,Wing Fai Loke,Ronghua Ni,Thomas Byunghak Cho

2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)（2017）

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Abstract

Digital PLL design challenges for cellular RFICs are presented. 5 digital PLLs are integrated in 28nm CMOS to support 3-Rx carrier aggregation (CA)/2-TxCA of FD-LTE/TD-LTE, GSM/EDGE, WCDMA/HSPA, and TD-SCDMA. The 400 kHz fractional spur of GSM/EDGE Tx LO is < −68 dBc for all channels. The integrated phase noise (IPN) degradation due to DCO-to-DCO coupling is < 0.5 dB even if two fractional PLLs are locked at same frequency.

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Key words

Digiatl PLL,RFIC,Cellular,LTE,GMS,WCDMA

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