A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology
2017 Symposium on VLSI Circuits(2017)
Abstract
An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than 1 zA (10
-21
A) was fabricated. In the 2T1C gain cell, an OSFET for the write operation was stacked over a SiFET for the read operation. The 1 Mbit macro was fabricated using a combination of 60-nm OSFET and 65-nm CMOS processes. It achieves a 140 MHz operation and data retention of more than 1 h. Its static power in the standby state and active power are 31 μW and 64 μW/MHz, respectively. The macro with long-term data retention can reduce the static power by power gating. 2T1C OSFET-based embedded memory is applicable to devices requiring high performance as well as low power.
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Key words
indium-gallium-zinc oxide transistor,CMOS logic process technology,embedded 1 Mbit 2T1C gain-cell memory macro,indium-gallium-zinc oxide semiconductor FET,off-state current,OSFET,write operation,SiFET,read operation,data retention,standby state,active power,static power reduction,power gating,2T1C OSFET-based embedded memory,frequency 140 MHz,size 65 nm,size 60 nm,InGaZnO
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