A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

2017 Symposium on VLSI Circuits(2017)

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摘要
A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2 nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.
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关键词
NAND flash memory,multichip package,F-chip,low-power storage applications,dual bidirectional transceiver architecture,data retiming technique,data training technique,signal integrity,I-O power consumption,voltage 1.2 V
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