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Sige Finfet for Practical Logic Libraries by Mitigating Local Layout Effect

Gen Tsutsui,Huimei Zhou,Andrew Greene,Robert Robison,Jie Yang,Juntao Li,Christopher Prindle,John R. Sporre,Eric R. Miller,Derrick Liu,Ryan Sporer,Bob Mulfinger, Tim McArdle,Jin Cho,Gauri Karve,Fee Li Lie, Siva Kanakasabapathy,Rick Carter,Dinesh Gupta,Andreas Knorr,Dechao Guo,Huiming Bu

2017 SYMPOSIUM ON VLSI TECHNOLOGY（2017）

引用 9|浏览108
关键词
SiGe FinFET insertion,fin cut process,channel strain relaxation,reliability benefit,DC performance,epitaxial defectivity control,local layout effect mitigation,logic libraries,SiGe CMOS FinFET,size 10 nm,SiGe
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