A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS

Kyoung-Jun Moon,Hyun-Wook Kang,Dong-Shin Jo,Mi-Young Kim,Seung-Yeob Baek,Michael Choi,Hyung-Jong Ko,Seung-Tak Ryu

2017 SYMPOSIUM ON VLSI CIRCUITS（2017）

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摘要

A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.

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关键词

single-channel pipelined SAR ADC,gm-cell residue amplifier,current-mode fine SAR ADC,CMOS process,background offset,gain calibration,word length 10 bit,size 28 nm,voltage 1 V,power 6 mW

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