Reliability of 2T-core CMOS OTP non-volatile memory bitcells

Reliability assessment on 2T CMOS antifuse bitcell, consisting of two core NMOSFETs having a program transistor coupled in series with a select transistor, is presented. The discrepancy in the measured time to breakdown of program transistors and predicted minimum programming voltage by discrete device based time dependent dielectric breakdown model, is identified to be directly related to the select transistor sizing. In addition, the maximum programming voltage is controlled by junction leakage between the middle node of program/select transistors and substrate while the unprogramed/inhibit stage is in the programming stress. Using these two critical findings, for the first time, this paper presents a scientific frame work to aid designer and manufacturer to fine tune their design/process and produce robust memory elements and IP blocks.