The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping

IEEE Transactions on Electron Devices(2017)

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Abstract
As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profil...
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Key words
Impurities,Logic gates,Silicon,Electric variables,Doping,Rapid thermal annealing
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