Quantifying metrics for analyzing integrated circuit design integrity

This work proposes an approach to quantifying the integrity of a questionable design by parsing it into four subdomains: Logical Equivalence, Signal Rate, Functional Correctness, and Power Consumption. Measurement techniques are presented for each domain that quantifies deviation of the actual design away from the expected performance. The domains are then aggregated together to arrive at a Figure of Deviation value that is indicative of the deviation of the actual design from its specification. The analysis technique was then applied to six Test Article (TA) cases that showed TA1 and TA5 to have the highest integrity (4.0) with 0% deviation and TA4 having the lowest integrity (1.99) with a 50.25% deviation from the expected performance.