SiGe HBT with fx/fmax of 505 GHz/720 GHz
2016 IEEE International Electron Devices Meeting (IEDM)（2016）
摘要
An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.
更多查看译文
关键词
HBT technology,minimum CML ring oscillator gate delay,emitter resistance,millisecond annealing,low-temperature back end,lateral device scaling,frequency 505 GHz,frequency 720 GHz,voltage 1.6 V,time 1.34 ps,SiGe
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要