High Rate LDPC Based Decoder Architectures with High Speed ADC for C-RAN Optical Fronthaul
2016 International Conference on Computer and Communication Engineering (ICCCE)(2016)
Abstract
In this paper we study the design of LDPC decoding scheme for very high throughput optical communications for a full self-seeded optical architecture dedicated to cloud radio access network (C-RAN). The objective of this paper is to demonstrate the potentiality of Bit Flipping (BF) algorithms. It is shown that the Gradient Descent Bit Flipping (GDBF) algorithm with a little improvement is suitable for high speed applications. With a simple high-speed two-bit Analog to Digital Convertor (ADC) we show that we can obtain a BER of as low as 10-9 for an input BER of 10-4. Furthermore, the proposed decoder achieves a BER of at least 10-7 after just one iteration. It is necessary for real time applications to reduce the decoding delay. We propose a simple FPGA implementation that gives 500 Mb/s. The guidelines are also suggested to increase the throughput up to 2.5 Gb/s, required by CRAN application.
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Key words
LDPC,FEC,C-RAN,hard decision,fronthaul,FPGA
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