A 12-bit 60-MS/s 36-mW SHA-less opamp-sharing pipeline ADC in 130 nm CMOS

This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter (ADC) implemented in a 0.13-mu m CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier (OTA) with an overlapping two-phase clocking scheme is proposed to achieve low power consumption and eliminate the non-resetting and memory effects observed in conventional opamp-sharing techniques. To further reduce the power consumption, the ADC also incorporates a SHA-less multi-bit structure. The ADC achieves a signal-to-noise and distortion ratio of 64.9 dB and a spurious-free dynamic range of 77.1 dB at 60 MS/s. It occupies 2.3 mm(2) of area and consumes 36 mW of power under a 1.2-V supply.