Accompanied arrangement effect of stretched gate width and dummy diffusion region on strained silicon PMOSFETs

When the size down to nanometer scale, different layout pattern effect to enhance device performance with advanced strain engineering. Protruded portion outside the channel region located on the soft STI A long gate width direction and across the dummy active region is preferable in the manufacture of transistors. For this reason, a 22 nm pMOSFET of silicon-based with S/D stressors Si ₇₅ Ge ₂ 5 alloy and a -2.0 GPa compressive CESL at different protruded gate widths is used to the investigation. Through the assistance of stress simulation, the stress contours and mobility gain of the nanoscale devices are estimated and analyzed. The maximum mobility gain was attained to 111.42 % with a 150 nm protruded gate width. The layout pattern design of nanoscale devices is important in the enhancement of device mobility.