A 2Gbps 21ch low-latency transceiver circuit for inter-processor communication

Toshio Tanahashi, Masakazu Kurisu,Hiroshi Yamaguchi,Takaaki Nedachi, Tsutomu Matsuzaki,Muneo Fukaishi

NEC RESEARCH & DEVELOPMENT（2002）

Cited 23|Views1

No score

Abstract

A 20-data-channel transceiver with a control channel allows uncoded data transfer with 13ns latency. A digital DLL (Delay Locked Loop) with a ring-interpolator tracks phase with 20ps resolution. A pre-emphasis driver enables 2Gbps transmission per channel over a 7m cable at 1.5V supply. The effective full-duplex bandwidth reaches 10GB/s.

Translated text

Key words

multi-channel serial interface,inter-processor communication,digital DLL (Delay Locked Loop),ring-interpolator,pre-emphasis,low latency

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined