An all-digital on-chip clock generator using relative reference modeling

An all-digital on-chip clock generator is proposed in this paper. It features the tolerance of process, voltage and temperature variation according to the special algorithm. The clock generator depends on CMOS standard delay cell without any external clock source, and the periods of CMOS standard delay cell are calculated by the linear polynomial fitting. The proposed on-chip clock generator has been implemented in 180 nm CMOS. The output clock is 10MHz~40MHz adjustable, and tolerates the process, voltage and temperature variation. The frequency error is less than 2.9% with 1.6V-1.8V supply voltage and 0°C-80°C temperature variation. The phase noise is -116.44 dBc/Hz @ 25 MHz offset.