Comprehensive investigation on array-type dummy active diffused region and gate geometries using narrow NMOSFETs with SiC S/D stressors

This study aims to investigate the combined strain effects of a dummy active diffused region (OD) and the salient gate width of a layout pattern on the mobility gain of a nanoscale device while considering the advanced stressors of a source/drain embedded silicon-carbon alloy with a 1.65% fraction mole of carbon and a contact etch stop layer with a tensile stress 1.0 GPa. To achieve this objective, we used a validated fabricationoriented stress-simulated methodology to estimate the performance of a 22 nm n-type metal-oxide-semiconductor field-effect transistor. In addition, the important design factors of the device layout, including dummy OD width as well as the shallow trench isolation (STI) gap between the short channel device and the dummy OD, are parametrically analysed. Consequently, the mobility gains with different types of layout pattern considered in this study are acquired through the estimated relationship between the stress components of the device channel and silicon-based piezoresistance coefficients. The analytical results indicate that device performance improves depending on the layout pattern, such as the adoption of a small salient gate width, huge dummy OD regions, and a small STI gap.