Fabrication of Sub-10 nm Metal Wire Circuits using Directed Self-Assembly of Block Copolymers

A novel half-pitch (HP) 10 nm physical-epitaxial frequency multiplication process using a high chi (chi) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrically open and short process level-test element group (PL-TEG) yield verification of sub-10 nm metal wire circuits fabricated using the HP 10 nm physical-epitaxial frequency multiplication process was carried out on a 300 mm wafer. The electrically open and short PL-TEG yield verification revealed the viability of the HP 10 nm physical-epitaxial frequency multiplication process from the perspective of the total practical performance including critical dimension control, defect control, pattern placement error, space width roughness, space edge roughness, and process windows in the pattern transfer process.