Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NAND flash memory's reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive VRef shift (AVS) and VTH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (VRef) based on temperature, W/E cycles and retention-time. AVS stores the optimal VRef's in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between VTH states. DVO reduces BER by 80%. (C) 2016 The Japan Society of Applied Physics