Parameters influencing unwanted growth during epitaxial growth of SiGe

In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of "Unwanted Growth" defects on wafers in the form of small SiGe nodules (20–50nm) left over post selective SiGe epitaxial growth for strained CMOS Si. These defects, depending on where they grow/land, can lead to failure of the chip. An optimization of the processing parameters to minimize the occurrence of these defects leads to yield gain and cost savings for High Volume Manufacturing (HVM).