Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture

Device characteristics of single-gate vertical channel (SGVC) 3D NAND architecture are discussed in detail. The most important feature of SGVC is that the memory cell is a flat-channel device in 3D, different from the more often used gate-all-around (GAA) macaroni cell. Through various device optimizations, we have successfully produced excellent cell initial performances and more than 10V peak P/E window for each memory cell. In sharp contrast to the GAA cell, the SGVC flat cell naturally has superior layer-to-layer device uniformity that tolerates non-ideal vertical etching. Memory window managements in MLC and TLC applications are discussed. It is found that the major interference factor comes from the WL to WL interference. The root cause of WL interference is identified to be the channel potential interaction between the selected gate and neighbor WL in a junction-free 3D NAND. Random grain boundary trap effect further deteriorates the WL interference. It is found that the commonly adopted WL iterating algorithms in conventional FG NAND is also suitable for our SGVC 3D NAND to provide very tight Vt distribution for MLC and TLC applications.