An analysis of power supply induced jitter for a voltage mode driver in high speed serial links

Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.