NMOS contact engineering for CMOS scaling

K. V. Rao,Chi-Nung Ni,Fareen Adeni Khaja,Xuebin Li,Shashank Sharma,Raymond Hung,Michael Chudzik,Bingxi Wood,Kyu-Ha Shim,Todd Henry,Naushad Variam

2015 15th International Workshop on Junction Technology (IWJT)（2015）

Cited 2|Views84

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Abstract

The 10-7 nm CMOS nodes require that ρc be reduced to <; 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

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Key words

NMOS,CMOS,Fermi level,Schottky barrier height,thermal implants,FinFET doping,size 10 nm to 7 nm

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