Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors
2014 IEEE International Nanoelectronics Conference (INEC)(2014)
摘要
To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.
更多查看译文
关键词
SiC stressor,Layout pattern effect,Lattice-mismatch strained engineering,Stress simulation,Mobility gain estimation
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要