Modeling and analysis of the HPM pulse-width upset effect on CMOS inverter*

We derive analytical models of the excess carrier density distribution and the HPM (high-power microwave) upset susceptibility with dependence of pulse-width, which are validated by the simulated results and experimental data. Mechanism analysis and model derivation verify that the excess carriers dominate the current amplification process of the latch-up. Our results reveal that the excess carrier density distribution in P-substrate behaves as pulse-width dependence. The HPM upset voltage threshold Vp decreases with the incremental pulse-width, while there is an inflection point which is caused because the excess carrier accumulation in the P-substrate will be suppressed over time. For the first time, the physical essence of the HPM pulse-width upset effect is proposed to be the excess carrier accumulation effect. Validation concludes that the Vp model is capable of giving a reliable and accurate prediction to the HPM upset susceptibility of a CMOS inverter, which simultaneously considers technology information, ambient temperature, and layout parameters. From the model, the layout parameter LB has been demonstrated to have a significant impact on the pulse-width upset effect: a CMOS inverter with minor LB is more susceptible to HPM, which enables us to put forward hardening measures for inverters that are immune from the HPM upset.