500-V Silicon-On-Insulator Lateral IGBT With W-Shaped n-Typed Buffer and Composite p-Typed Collectors

A novel 500-V rated silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT), featuring a W-shaped n-typed buffer and p-typed composite collectors, is proposed for the first time in this paper. The composite collectors which consist of a high-doped p+ layer and a low-doped p− layer can maintain a high level of collector-side hole injection in ON-state; the low-doped p− layer combining with the W-shaped buffer provides a low barrier path for electron extraction during turn-off; thus, high current capability and high turn-off speed can be realized at the same time. The measurement results show that 67.3% decrease in turn-off time can be obtained at the expense of only 6.3% of current capability. Compared with the standard SOI-LIGBT, no additional processing steps or process modifications are required for the proposed SOI-LIGBT. The low-doped p− collector is formed simultaneously with the emitter-side p-well while the W-shaped buffer is formed by diffusion overlapping of two neighboring windows. At 125 °C, the proposed SOI-LIGBT exhibits an ON-state voltage drop of 2.48 V, a saturated current density of 420 A/cm ² , a turn-off time of <250 ns, and a short-circuit withstand time of $>4~\mu \text{s}$ , allowing significant improvements in power loss, operating frequency, and ruggedness for single-chip intelligent power ICs.