Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults

The progressive downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits, mainly due to the voltage scaling. As a manner to mitigate this problem, redundancy techniques are constantly applied. To perform an accurate analysis for circuit reliability, in order to choose the best design alternative and minimize the impact of these redundancy techniques in the circuit, the PTM method is one of the most precise alternative. In this paper, it is proposed an Add-on for the PTM technique to increase its accuracy, providing an analysis of Single Event Transient faults in transistor-level. The results shown that it is important to add a new level of information to the PTM technique in order to make possible the analysis of different circuit configurations that performs the same logic function to choose the best option in the design.