Comprehensive Device And Product Level Reliability Studies On Advanced Cmos Technologies Featuring 7nm High-K Metal Gate Finfet Transistors

In this study, a reliability study from device, circuit aging, and product reliability characterization is systematically presented for the state-of-the-art 7nm FinFETs. The Bias-Temperature Instability (BTI) and Hot Carrier Injection (HCI) for 7nm FinFET are compared with past 10nm FinFET devices, as well as the novel aging framework to estimate BTI recovery and self-heat effect in 7nm early circuit design. Moreover, the correlation between SRAM static noise margin (SNM) and BTI induced Vt drift consolidates the domination of initial Vt spread for SNM shift. A new At-Speed High-Temperature Operating Life (HTOL) test could be able to trigger the potential Vmin tailing in 7nm Logic products which indicates the weakness and offers a promising process improvement direction.