Approximate Comparator: Design and Analysis

As a new design paradigm, approximate computing techniques have drawn tremendous attentions from the very large scale integration (VLSI) design society in recent years. Approximate computing can significantly reduce the energy consumption and the area occupancy at the cost of sacrificing a little performance for some error-tolerant applications. In this paper, an area-efficient, low-power, and high-speed approximate comparator is proposed. Motivated by the existing work, the digits of the input numbers are divided into multiple sub-blocks to perform the comparison in a parallel way to reduce the critical path delay. While in each sub-block, an approach which is different from the existing work is exploit to perform the comparison. Numerical analysis shows that the proposed approximate comparator has a lower error rate than the prior approximate comparator, which is demonstrated by the extensive simulations. When implemented under the Taiwan Semiconductor Manufacturing Company (TSMC) 90nm technology, the implementation results show that the proposed approximate comparator is more efficient than the prior approximate comparator in terms of many basic and compound metrics, such as area, delay, power, and energy-delay-error rate product (EDERP).