A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)(2018)

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摘要
This paper demonstrates a signal analysis SoC consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the core and the accelerators are instances produced by novel generators that allow for a wide range of parameter configurations and rapid design space exploration. The signal processing chain consists of generated instances of a time-interleaved ADC followed by a digital tuner, FIR filter, polyphase filter, and FFT all connected to the processor via an AXI4 bus. The 5 mm × 5 mm chip is implemented in a 16 nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art ASICs prove that generators can produce competitive designs.
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关键词
ASIC,AXI4 bus,multirate signal analysis RISC-V SoC,radar receive processing,FinFET process,accelerator performing spectrometry,polyphase filter,FIR filter,time-interleaved ADC,signal processing chain,rapid design space exploration,fixed-function signal-processing accelerator,vector extensions,signal analysis SoC,size 16.0 nm,frequency 410.0 MHz,voltage 750.0 mV,power 600.0 mW,size 5.0 mm
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