FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
2018 28th International Conference on Field Programmable Logic and Applications (FPL)(2018)
摘要
This paper proposes an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC). The TLC requires only 7 SRAM cells and can be configured to implement one of several threshold functions. The proposed architecture is implemented in a 28nm FDSOI process, and is evaluated on standard benchmark circuits and several large complex function blocks. The results demonstrate an average reduction of 8.9% in register count, 15.4% in multiplexer count, 7% average reduction in Basic Logic Element (BLE) area, and 8.2% average reduction in BLE power, with a maximum decrease in register count up to 64%, BLE multiplexer count up to 68%, BLE Area up to 51.6% and BLE power up to 61.6% without loss in performance. We also show a reduction of 21% in the area of a tile.
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关键词
Threshold Logic, FPGA, Reconfigurable, FDSOI, 28nm, PNAND, Low Power, Low Area, High Performance
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