An Adaptive Closed-Loop Verification Approach In Uvm-Systemc For Ams Circuits

The growth in the number of transistors and the increased integration of analog functionality within current chips has added significant complexity to embedded systems. The differences in design and verification methodologies for digital and analog circuits in terms of abstraction levels presents a series of challenges for the project flow. A good practice for unifying this flow is the use of Hardware Description Languages (HDLs) for developing Analog Mixed Signal (AMS) circuit models. However, the verification process still faces some obstacles related to test automation in the analog domain, mainly concentrated in the stimuli generation and data coverage activities. In this work, we propose an adaptive approach for the functional verification of AMS circuits using the Universal Verification Methodology applied to the SystemC language (UVM-SystemC) using a feedback connection between the scoreboard and the driver. In order to demonstrate the advantages of this method, it is applied to the verification of subcomponents of an Analog-to-Digital Converter (ADC), which is based on a peripheral of a real System on Chip (SoC) device.