Development Of The Address In Real Time (Art) Data Driver Card (Addc) Test Procedures Of The New Small Wheel Upgrade Project

The upgrades of the LHC accelerator will increase the instantaneous and the integrated luminosity during the data taking in 2019/20 and 2023/24, thus causing increased data and trigger rates. In order to cope with the increased muon rate while maintaining high muon detection efficiency the current ATLAS small wheel muon detectors will be replaced with a New Small Wheel (NSW) for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive MicroMegas and small strip Thin Gap Chambers with a total of 2.4 million readout channels. The MicroMegas and TGCs will have common readout paths but separate trigger paths. For the MicroMegas detector, the trigger primitive is the Address in Real Time (ART) signal. The ART Data Driver Card (ADDC) is designed for the MicroMegas detector to process and transmit the trigger data from the front end ASICs to the trigger processor. The ADDC will be located on the detector alongside the front-end electronics, while the trigger processor will be placed away from the high radiation and magnetic field environment. Therefore, it is crucial to thoroughly test the ADDC, since access will be difficult and limited once the NSW is installed. In order to perform a realistic test a dedicated firmware has been developed for the VC707 evaluation card, capable of generating ART signals and reading the ADDC card response that is send to the trigger processor. The FPGA can validate the ADDC response in real time and signify any errors found. A software library has also been developed, in order to control and monitor the test setup using a computer. Finally, a user interface will be developed to simplify and automate the test process.