A Charge-Based Architecture For Energy-Efficient Vector-Vector Multiplication In 65nm Cmos

In this work, a charge-based energy-efficient architecture for computing vector-vector multiplications (VVM) is presented. Using an array of capacitors, the inner product of vectors is quantitatively computed as the total charge injected onto the array. By scaling the capacitance to the thermal noise (kTC) limit, this computation can be done efficiently on the order of a few picoJoules (pJ). Furthermore, this charge is then converted into a pulse-density modulated binary output over time through a first-order delta-sigma converter, giving a trade-off of output precision and computation time. This design was fabricated in a 65nm CMOS process and measured to compute 6-bit MACs with a throughput of 350KOPs, and an overall efficiency of 14.6GOP/W at 5-bit precision. Moreover, the computation done on the array in the analog domain, has an efficiency of 284.4GOP/W.